verilog HDLBits刷题[Shift Registers]“Exams/m2014 q4k”---Shift register

1、题目2、代码module top_module ( input clk, input resetn, // synchronous reset input in, output out); reg Q1,Q2,Q3; always(posedge clk)begin if(!resetn)begin Q11b0; Q21b0; Q31b0; out1b0; end else begin Q1in; Q2Q1; Q3Q2; outQ3; end end endmodule